View CS8126D_6421031.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2001 january, 2001 rev. 11 1 publication order number: cs8126/d cs8126 5.0 v, 750 ma low dropout linear regulator with delayed reset the cs8126 is a low dropout, high current 5.0 v linear regulator. it is an improved replacement for the cs8156. improvements include higher accuracy, tighter saturation control, better supply rejection, and enhanced reset circuitry. familiar pnp regulator features such as reverse battery protection, overvoltage shutdown, thermal shutdown, and current limit make the cs8126 suitable for use in automotive and battery operated equipment. additional onchip filtering has been included to enhance rejection of high frequency transients on all external leads. an active microprocessor reset function is included onchip with externally programmable delay time. during powerup, or after detection of any error in the regulated output, the reset lead will remain in the low state for the duration of the delay. types of errors include short circuit, low input voltage, overvoltage shutdown, thermal shutdown, or others that cause the output to become unregulated. this function is independent of the input voltage and will function correctly with an output voltage as low as 1.0 v. hysteresis is included in both the reset and delay comparators for enhanced noise immunity. a latching discharge circuit is used to discharge the delay capacitor, even when triggered by a relatively short fault condition. this circuit improves upon the commonly used scr structure by providing full capacitor discharge (0.2 v type). note: the cs8126 is lead compatible with the lm2927 and lm2926. features ? low dropout voltage (0.6 v at 0.5 a) ? 3.0% output accuracy ? active reset ? external reset delay for reset ? protection circuitry reverse battery protection +60 v, 50 v peak transient voltage short circuit protection internal thermal overload protection http://onsemi.com to220 five lead t suffix case 314d 1 5 to220 five lead tva suffix case 314k to220 five lead tha suffix case 314a 1 5 1 pin 1. v in 2. v out 3. gnd 4. delay 5. reset to220 five lead the suffix case 314j 1 7 d 2 pak 7pin dps suffix case 936h pin 1. v in 2. v out 3. v out(sense) 4. gnd 5. delay 6. reset 7. nc 1 16 so16l d suffix case 751b see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information see general marking information in the device marking section on page 9 of this data sheet. device marking information 1 5
cs8126 http://onsemi.com 2 pin connections so16l nc delay 1 16 nc nc gnd reset nc nc nc nc v out(sense) nc nc nc v out v in delay qs r latching discharge + v discharge charge current generator + thermal shutdown bandgap reference + antisaturation and current limit + gnd reset preregulator regulated supply for circuit bias v out over voltage shutdown v in error amp delay comparator reset comparator figure 1. block diagram
cs8126 http://onsemi.com 3 absolute maximum ratings* rating value unit power dissipation internally limited peak transient voltage (46 v load dump) 50, 60 v output current internally limited esd susceptibility (human body model) 4.0 kv junction temperature range 40 to +150 c storage temperature range 55 to +150 c lead temperature soldering: wave solder (through hole styles only) (note 1.) reflow (smd styles only) (note 2.) 260 peak 230 peak c c 1. 10 second maximum. 2. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. electrical characteristics (t a = 40 c to +125 c, t j = 40 c to +150 c, v in = 6.0 to 26 v, i o = 5.0 to 500 ma, r reset = 4.7 k w to v cc , unless otherwise noted.) characteristic test conditions min typ max unit output stage (v out ) output voltage 4.85 5.00 5.15 v dropout voltage i out1 = 500 ma 0.35 0.60 v supply current i out 10 ma i out 100 ma i out 500 ma 2.0 6.0 55 7.0 12 100 ma ma ma line regulation v in = 6.0 to 26 v, i out = 50 ma 5.0 50 mv load regulation i out = 50 to 500 ma, v in = 14 v 10 50 mv ripple rejection f = 120 hz, v in = 7.0 to 17 v, i out = 250 ma 54 75 db current limit 0.75 1.20 a overvoltage shutdown 32 40 v maximum line transient v out 5.5 v 95 v reverse polarity input voltage dc v out 0.6 v, 10 w load 15 30 v reverse polarity input voltage transient 1.0% duty cycle, t < 100 ms, 10 w load 80 v thermal shutdown note 3. 150 180 210 c 3. guaranteed by design
cs8126 http://onsemi.com 4 electrical characteristics (continued) (t a = 40 c to +125 c, t j = 40 c to +150 c, v in = 6.0 to 26 v, i o = 5.0 to 500 ma, r reset = 4.7 k w to v cc , unless otherwise noted.) characteristic unit max typ min test conditions reset and delay functions delay charge current v delay = 2.0 v 5.0 10 15 m a reset threshold v out increasing, v rt(on) v out decreasing, v rt(off) 4.65 4.50 4.90 4.70 v out 0.01 v out 0.15 v v reset hysteresis v rh = v rt(on) v rt(off) 150 200 250 mv delay threshold charge, v dc(hi) discharge, v dc(lo) 3.25 2.85 3.50 3.10 3.75 3.35 v v delay hysteresis 200 400 800 mv reset output voltage low 1.0 v < v out < v rtl , 3.0 k w to v out 0.1 0.4 v reset output leakage current v out > v rt(on) 0 10 m a delay capacitor discharge voltage discharge latched aono, v out > v rt 0.2 0.5 v delay time c delay = 0.1 m f*. note 4. 16 32 48 ms * delay time c delay v delay threshold charge i charge c delay 3.2 10 5 (typ) 4. assumes ideal capacitor package lead description package lead # to220 5 lead d 2 pak 7pin so16l lead symbol function 1 1 1 v in unregulated supply voltage to ic. 2 2 16 v out regulated 5.0 v output. 3 4 11 gnd ground connection. 4 5 8 delay timing capacitor for reset function. 5 6 6 reset cmos/ttl compatible output lead. reset goes low after detec- tion of any error in the regulated output or during power up. 3 14 v out(sense) remote sensing of output voltage. 7 2, 3, 4, 5, 7, 9, 10, 12, 13, 15 nc no connection.
cs8126 http://onsemi.com 5 typical performance characteristics 0 v in (v) v in (v) i cq ( m a) figure 2. i cq vs. v in over temperature figure 3. i cq vs. v in over r load 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 55 50 45 40 35 30 25 20 15 10 5.0 120 110 100 90 80 70 60 50 40 30 20 10 v in (v) v out (v) figure 4. v out vs. v in over temperature 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 v in (v) v out (v) figure 5. v out vs. v in over r load i cq (ma) room temp. r load = 25 w r load = 25 w room temp. 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 25 c 125 c 40 c r load = 6.67 r load = 10 r load = 25 r load = no load 25 c 125 c 40 c r load = 10 r load = 6.67 r load = no load output current (ma) 0 100 200 300 400 500 600 700 800 100 80 60 40 20 0 20 40 60 80 100 output current (ma) 0 100 200 300 400 500 600 700 800 6.0 4.0 2.0 0 2.0 4.0 6.0 8.0 10 12 14 figure 6. line regulation vs. output current over temperature figure 7. load regulation vs. output current over temperature li ne r egu l at i on ( m v) load regulation (mv) temp = 25 c temp = 40 c temp = 125 c v in 6.026 v temp = 40 c temp = 25 c temp = 125 c v in = 14 v
cs8126 http://onsemi.com 6 typical performance characteristics (continued) output current (ma) 0 100 200 300 400 500 600 700 800 figure 8. dropout voltage vs. output current over temperature output current (ma) 0 100 200 300 400 500 600 700 800 100 90 80 70 60 50 40 30 20 10 0 figure 9. quiescent current vs. output current over temperature quiescent current (ma) 900 800 700 600 500 400 300 200 100 0 dropout voltage (mv) 90 80 70 60 50 40 30 20 10 0 rejection (db) freq. (hz) 10 0 figure 10. ripple rejection 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 output current (ma) figure 11. output capacitor esr 10 3 10 2 10 1 10 0 10 4 esr ( w ) 10 3 10 2 10 1 10 0 10 1 10 2 10 3 125 c 40 c 25 c 25 c 125 c 40 c cout = 10 mf, esr = 1 & 0.1 mf, esr = 0 c out = 10 m f, esr = 1 & 0.1 m f, esr = 0 c out = 10 m f, esr = 1.0 w c out = 10 m f, esr = 10 w c out = 47/68 m f c out = 47 m f c out = 68 m f stable region vin = 14 v v dc(lo) v dc(hi) v dh v rl delay (3) reset v rt(off) v rt(on) v rh (1) (2) (2) t delay v dis v out (1) = no delay capacitor (2) = with delay capacitor (3) = max:reset voltage (1.0 v) figure 12. reset circuit waveform reset circuit waveform
cs8126 http://onsemi.com 7 circuit description the cs8126 reset function, has hysteresis on both the reset and delay comparators, a latching delay capacitor discharge circuit, and operates down to 1.0 v. the reset circuit output is an open collector type with on and off parameters as specified. the reset output npn transistor is controlled by the two circuits described (see block diagram). low voltage inhibit circuit this circuit monitors output voltage, and when the output voltage falls below v rt(off) , causes the reset output transistor to be in the on (saturation) state. when the output voltage rises above v rt(on) , this circuit permits the reset output transistor to go into the off state if allowed by the reset delay circuit. reset delay circuit this circuit provides a programmable (by external capacitor) delay on the reset output lead. the delay lead provides source current to the external delay capacitor only when the alow voltage inhibito circuit indicates that output voltage is above v rt(on) . otherwise, the delay lead sinks current to ground (used to discharge the delay capacitor). the discharge current is latched on when the output voltage falls below v rt(off) . the delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. this feature ensures a controlled reset pulse is generated following detection of an error condition. the circuit allows the reset output transistor to go to the off (open) state only when the voltage on the delay lead is higher than v dc(h1) . the delay time for the reset function is calculated from the formula: delay time c delay v delay threshold i charge delay time c delay 3.2 10 5 if c delay = 0.1 m f, delay time (ms) = 32 ms 50%: i.e. 16 ms to 48 ms. the tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. application diagram figure 13. application diagram gnd v in v out cs8126 c 1 * 100 nf c 2 ** 10 m f to 100 m f * c 1 is required if the regulator is far from the power source filter. ** c 2 is required for stability. reset delay r rst 4.7 k w delay 0.1 m f application notes stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr, can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (25 c to 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c 2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. to determine an acceptable value for c 2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.
cs8126 http://onsemi.com 8 step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 14) is: p d(max) v in(max) v out(min) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current, for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can then be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 14. single output regulator with key performance parameters labeled smart regulator control features i out i in i q v in v out heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja . r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs8126 http://onsemi.com 9 ordering information device description shipping cs81261yt5 to220 five lead straight 50 units/rail cs81261ytva5 to220 five lead vertical 50 units/rail cs81261ytha5 to220 five lead horizontal 50 units/rail cs81261ythe5 to220 five lead surface mount 50 units/rail cs81261yther5 to220 five lead surface mount 750 tape & reel cs81261ydps7 d 2 pak, 7pin 50 units/rail cs81261ydpsr7 d 2 pak, 7pin 750 tape & reel cs81261ydw16 so16l 46 units/rail cs81261ydwr16 so16l 1000 tape & reel marking diagrams xxx... = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week to220 five lead t suffix case 314d xxxxxxxx awlyww 1 to220 five lead tva suffix case 314k xxxxxxxx awlyww 1 to220 five lead tha suffix case 314a xxxxxxxx awlyww 1 to220 five lead the suffix case 314j xxxxxxxx awlyww 1 d 2 pak 7pin dps suffix case 936h so16l d suffix case 751b xxxxxxxx awlyww 1 1 xxxxxxxxxx awlyww 16
cs8126 http://onsemi.com 10 package dimensions to220 five lead t suffix case 314d04 issue e q 12345 u k d g a b 5 pl j h l e c m q m 0.356 (0.014) t seating plane t dim min max min max millimeters inches a 0.572 0.613 14.529 15.570 b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 g 0.067 bsc 1.702 bsc h 0.087 0.112 2.210 2.845 j 0.015 0.025 0.381 0.635 k 0.990 1.045 25.146 26.543 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 u 0.105 0.117 2.667 2.972 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. to220 five lead tva suffix case 314k01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.78 10.54 c 0.160 0.190 4.06 4.83 d 0.027 0.037 0.69 0.94 e 0.045 0.055 1.14 1.40 f 0.530 0.545 13.46 13.84 g 0.067 bsc 1.70 bsc j 0.014 0.022 0.36 0.56 k 0.785 0.800 19.94 20.32 l 0.321 0.337 8.15 8.56 m 0.063 0.078 1.60 1.98 q 0.146 0.156 3.71 3.96 s 0.146 0.196 3.71 4.98 u 0.460 0.475 11.68 12.07 w 55 r 0.271 0.321 6.88 8.15 a u d g b t m 0.356 (0.014) m q 5 pl q k f j c e t s l 12345 seating plane r m w
cs8126 http://onsemi.com 11 to220 five lead tha suffix case 314a03 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 0.043 (1.092) maximum. dim a min max min max millimeters 0.572 0.613 14.529 15.570 inches b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 f 0.570 0.585 14.478 14.859 g 0.067 bsc 1.702 bsc j 0.015 0.025 0.381 0.635 k 0.730 0.745 18.542 18.923 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 s 0.210 0.260 5.334 6.604 u 0.468 0.505 11.888 12.827 t seating plane l s e c f k j optional chamfer 5x d 5x m p m 0.014 (0.356) t g a u b q p to220 five lead the suffix case 314j01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. 4. dimensions exclusive of mold flash and metal burrs. 5. footpad length measured from lead tip with reference to datum -m-. 6. coplanarity 0.004" max. reference to datum -n- standoff height 0.00 - 0.010". a u d g b t m 0.356 (0.014) m q 5 pl q k f j c e t l 12345 dim min max min max millimeters inches a 0.568 0.583 14.43 14.81 b 0.395 0.405 10.03 10.29 c 0.170 0.180 4.32 4.57 d 0.028 0.036 0.71 0.91 e 0.045 0.055 1.14 1.40 f 0.543 0.558 13.79 14.17 g 0.067 bsc 1.70 bsc j 0.014 0.022 0.36 0.56 k 0.073 0.088 1.85 2.24 l 0.324 0.339 8.23 8.61 q 0.146 0.156 3.71 3.96 s 0.000 0.010 0.00 0.25 u 0.460 0.475 11.68 12.07 seating plane w m 0.102 (0.004) n s w 5 5
cs8126 http://onsemi.com 12 d 2 pak 7pin dps suffix case 936h01 issue o t dim min max min max millimeters inches a 0.326 0.336 8.28 8.53 b 0.396 0.406 10.05 10.31 c 0.170 0.180 4.31 4.57 d 0.026 0.036 0.66 0.91 e 0.045 0.055 1.14 1.40 f 0.058 0.078 1.41 1.98 g 0.050 bsc 1.27 bsc h 0.100 0.110 2.54 2.79 j 0.018 0.025 0.46 0.64 k 0.204 0.214 5.18 5.44 m 0.055 0.066 1.40 1.68 n 0.000 0.004 0.00 0.10 notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions b and m. 4. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) max. b n a k m e c seating plane f h j d 7 pl g t m 0.13 (0.005) m b 12345 u 0.256 ref 6.50 ref v 0.305 ref 7.75 ref 67 8 u v so16l d suffix case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
cs8126 http://onsemi.com 13 package thermal data parameter to220 five lead d 2 pak 7pin so16l unit r q jc typical 2.1 2.1 23 c/w r q ja typical 50 1050* 105 c/w *depending on thermal properties of sustrate. r q ja = r q jc + r q ca.
cs8126 http://onsemi.com 14 notes
cs8126 http://onsemi.com 15 notes
cs8126 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8126/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

▲Up To Search▲

Price & Availability of CS8126D

	To Download CS8126D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .